I2C Transaction Patterns
This page was last modified 2007-03-28 20:41:04 by Puchu.Net user Choco. (Show history)



I2C is a bus protocol frequently used among IC chips to control devices on the I2C bus. Two signals, the clock (SCL) and data (SDA) are present on the I2C bus.

On the bus, there are always master and slave devices. In case there are multiple devices, an address is used to identify which device the master wants to communicate with.

Symbol Definitions

S start condition (SDA transition from high to low when SCL is high)
X stop condition (SDA transition from low to high when SCL is high)
A ack, acknowledge previous word (high)
NA noack (low)
R read mode (high)
W write mode (low)

The following background colors are used to distinguish origin of data on I2C bus:

bits transmitted by master
bits transmitted by slave

Master Send

Master sends data to slave at address:

S addr W A data A data A ... data A data A X

Master Receive

Master receives data from slave at address:

S addr R A data A data A ... data A data NA X

Combined Transaction

Combined (in this example, read then write) transaction allows multiple transactions without issuing the stop condition. If stop condition is issued, another device may take over the bus, or there may be additional setup time.

Instead of a stop condition, a start condition is generated to continue combined transaction.

S addr R A data A ... data A data NA S addr W A data A ... data A data A X


I2C address can be 7 bits or 10 bits wide. Often for an IC, each access to the bus is one byte; the read and write bit take up the last bit, so that you transfer different data to read or write. For example, transfer 0x20 to write and 0x21 to read. Read the datasheet of your IC to determine what is being requested.


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